1. Field of the Invention
The present invention relates to techniques for improving the performance of computer systems. More specifically, the present invention relates to a method and an apparatus for eliminating the restart penalty when reissuing deferred instructions.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two cache or main memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers that are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.
Some processor designers have proposed utilizing an execute-ahead mode to avoid cache-miss delays. During a normal-execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order.
When the unresolved data dependency is resolved during execute-ahead mode, the system enters a deferred execution mode, wherein the system executes deferred instructions. If all deferred instructions are executed during this deferred execution mode, the system returns to normal-execution mode to resume normal program execution from the point where the execute-ahead mode left off.
By continuing to perform work while waiting for cache misses to return, the execute-ahead mode can significantly increase the amount of work that can be completed by a processor.
When the processor enters deferred mode from execute-ahead mode, there presently exists a restart penalty because deferred instructions must be introduced into the pipeline at a stage where they can read the Architectural Register File (ARF) to obtain source operands. Since the ARF is read during the decode stage of the in-order processor, the deferred instruction must enter the pipeline prior to the decode stage. Consequently, the execution of the first deferred instruction will be delayed by the number of cycles it takes to get the first deferred instruction through the decode stage.
Hence, what is needed is a method and an apparatus for avoiding the restart penalty when entering deferred mode from execute-ahead mode.